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Features
1.4 Features
The Freescale DSP56311, a member of the DSP56300 core family of programmable DSPs,
supports wireless infrastructure applications with general filtering operations. Like the other
family members, the DSP56311 uses a high-performance, single-clock-cycle- per-instruction
engine (code compatible with Freescale's popular DSP56000 core family), a barrel shifter, 24-bit
addressing, instruction cache, and DMA controller. The DSP56311 offers 150 million
instructions per second (MIPS) performance (300 MIPS using the EFCOP in filtering
applications) using an internal 150 MHz clock with 3.3 V core and input/output (I/O) power.
All DSP56300 core family members contain the DSP56300 core and additional modules. The
modules are chosen from a library of standard predesigned elements, such as memories and
peripherals. New modules can be added to the library to meet customer specifications. A standard
interface between the DSP56300 core and the internal memory and peripherals supports a wide
variety of memory and peripheral configurations. In particular, the DSP56311 includes a JTAG
port integrated with the Freescale OnCE module.
The DSP56311. with its large internal memory arrary of 128 K words and its EFCOP, is well
suited for high-end multichannel telecommunication applications, such as multi-line
voice/data/fax processing, video conferencing, and general digital signal processing
1.5 DSP56300 Core
Core features are fully described in the DSP56300 Family Manual. This manual, in contrast,
documents pinout, memory, and peripheral features. Core features are as follows:
150 MIPS (300 MIPS using the EFCOP in filtering applications) with a 150 MHz clock at
1.8 V
Highly parallel instruction set
Data arithmetic logic unit (Data ALU)
— Fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC)
— 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
— Conditional ALU instructions
— 24-bit or 16-bit arithmetic support under software control
Program control unit (PCU)
— Position Independent Code (PIC) support
— Addressing modes optimized for DSP applications (including immediate offsets)
— Instruction cache controller
— Internal memory-expandable hardware stack
— Nested hardware DO loops
— Fast auto-return interrupts
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
1-5
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